New metrology measurement and lithography control methodologies for overlay control of integrated circuit fields within and between circuit layers made by a lithographic process are described in U.S. Pat. No. 5,877,861. As described therein, exposure tools known as steppers print multiple integrated circuit patterns or fields (also known as product cells) by lithographic methods on successive layers of a semiconductor wafer. These steppers typically pattern different layers by applying step and repeat lithographic exposure or step and scan lithographic exposure in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits. The stepper achieves registration among pattern layers by aligning the current layer to a previously patterned layer.
Overlay measurement determines the relative positioning errors among patterns on the same or different layers subsequent to the lithographic patterning process. Overlay measurement is critical to achieving the nanometer-scale positioning of patterns across multiple process layers necessary for advanced semiconductor manufacturing. Successful overlay refers to a condition where the relative locations of patterns throughout the sequence of manufactured layers that comprise the finished circuit correspond to the desired circuit design within allowed tolerances. Currently, overlay measurement is performed using targets comprised of nested sub-patterns printed together with the functional circuit elements at each successive lithographic step. Images of the overlay targets are captured by an imaging system. Algorithms applied to the captured images extract the relative displacement of the nested sub-patterns. The resulting overlay error is typically expressed as the vector sum of the (x, y) components of the relative displacement.
In the most common overlay target designs the sub-patterns are square; often referred to as “box-in-box,” “frame-in-frame” or “bar-in-bar” targets. A frame-in-frame example is shown in FIG. 1. By convention the target is comprised of an outer “reference” sub-pattern 1a and an inner “post” sub-pattern 1b, where the post sub-pattern is printed after the reference sub-pattern. The overlay error is defined as the displacement of the post sub-pattern relative to the reference sub-pattern. Nesting among more than two square sub-patterns to accommodate more than one pair of layers has been disclosed by Leidy et al. in U.S. Pat. No. 6,350,548.
Designs and analysis methods for overlay targets based on various array sub-patterns, consisting of periodic pattern elements, have also been disclosed. For example, Ross et al. in U.S. Pat. Nos. 6,061,606 and 6,457,169 discloses using the phase shift between adjacent circuit and circuit-like arrays as an overlay metric. Ausschnitt in U.S. patent application Ser. No. 09/678,634 discloses interleaved arrays of slightly different spatial frequency to produce a synthetic beat signal that amplifies the measurable effect of overlay error. Adel et. al., in International Publication Number WO 02/19415 discloses diagonally opposed and spatially offset arrays measurable by the pattern phase shift in a manner similar to that described by Ross.
The ideal overlay target must be optimized over various constraints: 1) To maximize the productive space on each manufactured wafer (the area occupied by functional circuit elements) the overlay target must be as small as possible. 2) To maximize overlay measurement capability, the sub-patterns that comprise the overlay target must be as large and dense as possible, having nearly equal size and density among all sub-patterns. 3) To minimize image interference effects, the sub-patterns must be as widely separated as possible. 4) To minimize tool induced shift (TIS) effects, the target must enable compensation for errors introduced by the imaging system distortion across the image field of view (FOV). 5) To minimize measurement time, the overlay target must enable simultaneous measurement among multiple sub-pattern pairs. 6) To eliminate error in associating the sub-pattern pairs with the correct process layers and exposure fields, each sub-pattern must have a unique identifier. 7) To optimize alignment control, the overlay target nesting must be tailored to the product alignment tree (in which each branch is the sequence of layers that align to a common reference layer). 8) To ensure robust imaging and process insensitivity, the sub-patterns must be compatible with the ground-rules of the layers on which they are printed.
While the overlay targets described by the prior art individually meet some of the above criteria, there is still a need for an overlay target that is optimized over the full set of constraints.